Design Engineer II
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Experience: 2 - 4 Years. Skills Expected: Strong Verilog, SVA and Formal environment development skills with working knowledge of any High Speed Interface protocols like AMBA/USB/PCIe/CXL/UCIe/UALink/Ethernet. Having experience in Formal Verification is mandatory. Develop detailed formal verification test plans based on design specifications and collaborate with...