Senior Engineer (Level 1)- Verification

eInfochips · Bangalore, IN

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Position: Senior Engineer (Level 1)- Verification Job Description: Roles and Responsibilities: · 4 to 8 years of experience in SOC/IP/block level functional verification using System Verilog/UVM. · Strong knowledge of UVM, advance UVM,System Verilog. · Must have worked on development of testplan, testbench components, verification environment, interface agents, Scoreboard in UVM. Understanding of complete functional verification cycle will be added advantage · Must have...