Mixed- Signal Systems and Verification Engineer
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Qualifications • New graduates strongly encouraged to apply! • Experience in developing and verifying real-numbered behavioral models in SystemVerilog • Understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS • Basic understanding of AMS blocks like filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer, etc • Working experience in low power Architecture...
- Perl
- Python