Design Engineer II
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Role Overview: Key Responsibilities: • Verification Infrastructure: Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments. • Advanced Verification: Champion the integration of formal verification, and AI-driven coverage analysis. • Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to...
- Perl
- Python
- C++